Mnemonic

MOV r$1,$ #$0$x$0004$A$000$

MOV r$2,$ #$0$x$00003$BC$0$

MOV ro$,$ r$1,$ LSL #$4$

SUB $r3,r2,r1$

ADDr$4,r1,r2$

RSB r$5,$ r$4,$ ro

MOV r$6,$ #$0$x$000002$E$4$

MOV r$7,$ #$0$x$0002$E$400$

ADD $r2,r1,r0$

Comment

; move $0$x$0004$A$000$ into r$1$

; move $0$x$00003$BC$0$ into r$2$

; left shift $r1$ by $4$ bits

; subtract $r1$ from $r2$

; add $r1$ and $r2,$ sum in $r4$

; subtract r$4$ from r$0$

; move $0$x$000002$E$4$ into r$6$

; move $0$x$0002$E$400$ into r$7$

; add $r1$ and $r0,$ sum in $r2$

c$)$ i$)$ Draw a pipeline diagram for the program given above in part b$),$

assuming that it is executed using the ARM$9$ microprocessor.

ii$)$ What is the performance, as measured in 'clocks per instruction'

$($CPI$)?($counting clock cycles from the execute stage of the first

instruction to the execute stage of the last instruction$)$

iii$)$ How can the instructions be reordered so that 'read$-$after$-$write' hazard

do not occur without changing the function of the programme?