Question: module calculator(in1,in2,opCode,result,overflow); input signed [15:0] in1; input signed [15:0] in2; input [3:0] opCode; output reg signed [15:0] result; output reg overflow; always @ (in1,in2) begin

module calculator(in1,in2,opCode,result,overflow);

input signed [15:0] in1; input signed [15:0] in2; input [3:0] opCode;

output reg signed [15:0] result; output reg overflow;

always @ (in1,in2) begin if (opCode == 4'b0000) //Add both inputs (0) begin if(in1+in2<=32767 || in1+in2>= -32768)begin overflow = 0; end end else begin overflow = 1; $monitor("in1=%b, in2=%b, Addition=%b, Overflow=%b",in1,in2,result,overflow); end end always @ (in1,in2,result) begin if (opCode == 4'b0001) //Subtract in1-in2 (1) begin if((result<=32767) || (result>= -32768))begin overflow = 0; end else begin overflow = 1; $monitor("in1=%b,in2=%b, Subtraction=%b, Overflow=%b",in1,in2,result,overflow); end end end always @ (in1,in2) begin if (opCode == 4'b0010) //Multiply in1 by five (2) begin if(in1*5<=32767 && in1*5>= -32768)begin if (result[15]==1) overflow = 0; end else begin overflow = 1; $monitor("in1=%b,in2=%b, Multiplication=%b; Overflow=%b",in1,in2,result,overflow); end end end always @ (in1,in2) begin if (opCode == 4'b0011) //Divide in1 by ten (3) begin if(in1%10 == 0 ) begin overflow = 1'b0;; end else begin overflow = 1'b1; end end end always @ (in1,in2) begin if(opCode == 4'b0100)begin //Bitwise AND (4) if((in1-1<= 32767) || (in1-1>= -32768)) begin overflow = 1'b0; end end end always @ (in1,in2,opCode) begin if(opCode == 4'b0101)begin //Bitwise XOR (5) if(in1^in2<=32767 || in1^in2>=-32768)begin overflow = 1'b0; end end end

always @ (in1,in2)begin if(opCode == 4'b0110)begin //Bitwise OR (6) if((in1 | in2<= 32767) || (in1 | in2>= -32768)) overflow = 1'b0; end else begin overflow = 1'b1; end end

always @ (in1,result) begin if(opCode == 4'b0111) //One's Complement in1 (7) if(((-(in1))-1<= 32767) || ((-(in1))-1>= -32768)) begin overflow = 1'b0; end end

always @ (in1,result)begin if(opCode == 4'b1000) //Increment in1 by 1 (8) begin if(in1+1<=32767 || in1+1>= -32768) begin overflow = 1'b0; end else begin overflow = 1'b1; end end end always @ (in1,result)begin if(opCode == 4'b1001) begin //Decrement in1 by 1 (9) if((in1-1<= 32767) || (in1-1>= -327698)) begin overflow = 1'b0; end else begin overflow = 1'b1; end end end

always @ (in1,in2,opCode) begin case(opCode)

4'b0000: result = in1 + in2; 4'b0001: result = in1 - in2; 4'b0010: result = in1 * 5; 4'b0011: result = in1 / 10; 4'b0100: {overflow,result} = in1 & in2; 4'b0101: {overflow,result} = in1 ^ in2; 4'b0110: {overflow,result} = in1 | in2; 4'b0111: {overflow,result} = (-(in1))-1; 4'b1000: {overflow,result} = in1 + 1; 4'b1001: {overflow,result} = in1 - 1; endcase end

endmodule

Need to account for overflow on positive and negative numbers. This is what I have so far.

Build a Verilog module named calculator that takes in two signed 16-bit numbers named in1 and in2 and performs the following functions depending on the value of another 4-bit input named opCode (see table below). Be aware that the opCode is not signed, like the inputs A and B of project 2. The outputs of the module calculator must be a signed 16-bit number named result, and a 1- bit overflow. Be aware that the value of overflow doesnt always get calculated the same way, it depends on the operation (see table below for more info and examples). The value of the output overflow will be one if an overflow occurred or the value of result is not completely accurate or correct; else the output overflow will be zero.

The syntax to declare buses as signed is: input signed [15:0] in1; output reg signed [15:0] result;

//Declaring outputs as reg will allow you to assign values to them

Also, be aware that unsigned N-bit registers can store values from 0 to 2N-1. While signed N-bit registers can store values from -2N-1 to 2N-1-1.

opCod e

Operation that has to be performed

0000

Add both inputs. Be aware that the overflow detection when adding and subtracting must be different than for Project 2 because in Project 2 the inputs were unsigned, while now for Project 3 the inputs are signed.

0001

Subtract in1 in2.

0010

Multiply in1 by five

0011

Divide in1 by ten. When dividing by ten, signal an overflow when in1 is not exactly divisible by ten. For instance, if in1=30, then result=3 and overflow=0; but if in1=35, then result=3 and overflow=1. You will need to explore the use of the percentage sign (%), which performs modulo operations (also known as modulus operator, https:// en.wikipedia.org/wiki/Modulo_operation ). The modulo finds the remainder of a division. If the remainder is zero then overflow=0; but if the remainder is not zero then produce overflow =1.

0100

Bitwise AND. Even though in1, in2 and result are declared as signed numbers, when applying the bitwise operations they are taken as raw bits. A bitwise operation (https://en.wikipedia.org/wiki/ Bitwise_operation ) is when the operation is applied to the individual bits. In this case, there will be an AND gate operation between the individual bits of in1 and the individual bits of in2; such that an AND logic will be applied to the first bit of in1 and the first bit of in2 and the output of that AND will be the first bit of result; an AND logic will be applied to the bit of position n of in1 and the bit of position n of in2 and the output of that AND will be the bit of position n of result; and so on. For example:

in1 = 1010110011110000

in2 = 1100101000110011 result = 1000100000110000

Bitwise AND, XOR and OR operations cant overflow, so overflow=0 by default.

0101

Bitwise XOR. Similar to explanation above, but with an XOR (also known as exclusive OR) operation instead. Example:

in1 = 1010110011110000

in2 = 1100101000110011 result = 0110011011000011

0110

Bitwise OR. Similar to explanation above, but with an XOR operation instead. Example:

in1 = 1010110011110000

in2 = 1100101000110011 result = 1110111011110011

0111

Ones Complement in1. Perform ones complement, by inverting bits (do not add one afterwards, because that would be twos complement). Complement operation cant overflow, so overflow=0 by default. Examples:

in1='b00000000000000; opCode='b0111; expectedOverflow='b0; result='b1111111111111111;

in1='b0000000000000001; opCode='b0111; expectedOverflow='b0; result='b1111111111111110;

1000

Increment in1 by 1. Examples: if in1=3, then result =4. If in1=-3, then result =-2.

1001

Decrement in1 by 1. Examples: if in1=3, then result =2. If in1=-3, then result =-4.

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