Multi$-$Level Cache:

$($Miss penalty$)L1=$ hit time $L2+$ miss rate $L2x$ miss penalty $L2$

The average memory access time $($AMAT$)$ for a microprocessor with $1$ level of cache is $2\mathrm{.}5$ clock cycles.

If data is present and valid in the cache, it can be found in $1$ clock cycle.

If data is not found in the cache, $90$ clock cycles are needed to get it from off$-$chip memory.

Designers are trying to improve the AMAT by making it $75\%$ of the original AMAT, and are considering adding a second level of cache on$-$chip.

This second level of cache could be accessed in $6$ clock cycles, and the addition of this cache does not affect the first level cache's access patterns or hit times. Off$-$chip accesses would still require $90$ clock cycles.

To obtain the desired speedup, how often must data be found $($i$.$e$.,$ hit rate$)$ in the $2$nd level cache?