Multiple choice question help

1. (10 pts) The single-cycle MIPS processor: (a) requires one clock cycle to process (i.e. fetch, decode, and execute) each instruction. (b) requires multiple clock cycles to process each instruction. (c) can process multiple instructions at the same time. (d) both (a) and (c). (e) None of the above.

2. (10 pts) The clock period for the single-cycle MIPS processor is determined by: (a) the amount of time the ALU needs to complete an ADD operation. (b) the amount of time required to access memory. (c) the instruction that requires the least amount of time.

   (d) the instruction that requires the most amount of time. (e) None of the above.

3. (10 pts) The One-bus implementation of the MIPS processor: (a) requires one clock cycle to process (i.e. fetch, decode, and execute) each instruction. (b) requires multiple clock cycles to process each instruction. (c) can process multiple instructions at the same time. (d) both (b) and (c). (e) None of the above.

4. (10 pts) The clock period for the One-bus implementation of the MIPS processor is determined by: (a) the amount of time the ALU needs to complete an ADD operation. (b) the instruction that requires the most amount of time.

   (c) the amount of time needed to complete the longest micro-operation. (d) the amount of time needed to complete the shortest micro-operation. (e) None of the above.

5. (10 pts) True or False: The control unit can be described using a finite state machine (FSM).