ND Q BME 328 Lab 6- VHDL for Sequential Circuits: Implementing a Customized State Machine 1. Objectives 5. 1 of 4 + Automatic Zoom 15 Marks (1 week) Due Date: Week 10 To simulate and verify the operation of a sequential circuit. To design a finite state machine (FSM) that cycles through the individual digits of your student ID using the assigned state diagrams. To learn the difference between Mealy and Moore machines and express the FSMs with different state assignments. 2. Pre-Lab Preparation 2. 1. You will be assigned one of the state machines described by the state diagrams shown in Figure 1. Your implementation will either be a Mealy or Moore state machin as assigned by your lab instructor. Produce a state table and state-assigned table for your customized state machine. 3. Design the logic equations for each of the Flip-Flop inputs described in Figure 2. 4. Draw the logic diagram either as Mealy or Moore state machine for your circuit (depending on the assignment by your lab instructo