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. For the given hypothetical structure of a computer, briely describe the instruction fetch and execute cycles. For execution of instruction identiy the corresponding modules (like PC, ALU) engaged in each of the cycles in the block diagram. Using RTL, describe sequence of steps t LDR F1,56, in fetch and execute cycles for execution of the given instruction. hat oceur (15 pta) Partial structure of a hypothetical stored program MAR Program Counter The operands fieks f the instnuction provides any source and destination operands required by the instruction Data path between mamay and registers from MBR memery in a Op-code Operands Memory tufter register cU Pati teken by the inst ution when it is logister rO Control ufetchjel from memory Register Fi Path for data flowing betweon memory (via thMBR), the Register r and the ALU ALU Condition code Q . For the given hypothetical structure of a computer, briely describe the instruction fetch and execute cycles. For execution of instruction identiy the corresponding modules (like PC, ALU) engaged in each of the cycles in the block diagram. Using RTL, describe sequence of steps t LDR F1,56, in fetch and execute cycles for execution of the given instruction. hat oceur (15 pta) Partial structure of a hypothetical stored program MAR Program Counter The operands fieks f the instnuction provides any source and destination operands required by the instruction Data path between mamay and registers from MBR memery in a Op-code Operands Memory tufter register cU Pati teken by the inst ution when it is logister rO Control ufetchjel from memory Register Fi Path for data flowing betweon memory (via thMBR), the Register r and the ALU ALU Condition code