Need help answering these questions. Please make it clear which question is being answered.

You are to determine the performa of a caching scheme. The specific caching system you are to simulate is determined nce significant) digi of your AAT ID number. In the table below check the by the last (least caching system that you will be simulati ID Mapping Algorithm Line size Check your algori Direct 4-5 Fully Associative 64 6-7 Fully Associative The cache has only 256 bytes. Memory addresses are 16 bits Binary address hit. length. If your caching system is fully associative or set associative, use a least recently used (LRU) replacement 1100 1110111011000101 algorithm. The cache is initially empty with no valid data s. [10 points] Show how the address is divided into fields and 0000011000010100 r6 0110 1000 specify the size of each field in bits 0000000101110110 7 01000001 8 1110111011001 110 9 0000000101000100 0111011010100 9. [12 points] In the table on the right are 24 memory addresses 11 01001001 of reads made by a computer system. Put a check in the 12 0000011000011110 column marked "hit" if this memory read will cause a cache 13 01000000 14 0000000101011110 10. [8 points] What is the hit rate of your simulated cache? 15 0000000101001111 16 0100000111010111 17 1110111011001000 0100000111001110 To complete this simulation, it is suggested that you make a 110111011011111 cache table with 4 rows (depending on your 19 or 8 caching scheme) 20 0100000110110110 that represent the tag field of the simulated cache. Separate the binary bits of the 24 addresses according to your mapping 1110111011000110 scheme. For each address, determine if this address is in cache. 22 010000011010101 If it is already in cache, but a check in the hit column. If it is not 23 000001 1001101111 in cache, save the tag address in your cache table 24 01000001 10100000 Page 3 of 3