Need just the screenshots for these working Quartus prime code

1. [5 points] Code screenshot of arrmul.sv file and upload the file separately. 2. [1 points] Screenshot of successful compilation of arrmul module. 3. [3 points] Screenshot of simulation result for the module. 4. [1 points] Screenshot of RTL Viewer of the module.

1. [4 points] Complete table for the testbench. 2. [6 points] Code screenshot of alu.sv file for alu and alu_tb modules and upload the file separately. 3. [1 points] Screenshot of successful compilation of alu module. 4. [3 points] Screenshot of simulation waveform and Transcript windows. 5. [1 points] Screenshot of RTL Viewer of the module.

Working Code:

/*

ECE 37100 Lab 2

Array multiplier for unsigned 4-bit inputs

Input: X 4-bit, Y 4-bit

Output: P 8-bit

*/

module halfadd(input logic a, b,

output logic s, c);

// Write your code

endmodule

module fulladd(input logic a, b, cin,

output logic s, cout);

// Write your code

endmodule

module arrmul(input logic[3:0] X,

input logic[3:0] Y,

output logic[7:0] P);

logic X3Y0, X2Y0, X1Y0, X0Y0;

assign X3Y0 = X[3] & Y[0];

assign X2Y0 = X[2] & Y[0];

assign X1Y0 = X[1] & Y[0];

logic X3Y1, X2Y1, X1Y1, X0Y1;

assign X3Y1 = X[3] & Y[1];

assign X2Y1 = X[2] & Y[1];

assign X1Y1 = X[1] & Y[1];

assign X0Y1 = X[0] & Y[1];

logic X3Y2, X2Y2, X1Y2, X0Y2;

assign X3Y2 = X[3] & Y[2];

assign X2Y2 = X[2] & Y[2];

assign X1Y2 = X[1] & Y[2];

assign X0Y2 = X[0] & Y[2];

logic X3Y3, X2Y3, X1Y3, X0Y3;

assign X3Y3 = X[3] & Y[3];

assign X2Y3 = X[2] & Y[3];

assign X1Y3 = X[1] & Y[3];

assign X0Y3 = X[0] & Y[3];

logic S10, S11, S12, S13;

halfadd s10(X1Y0, X0Y1, S10, C10);

fulladd s11(X2Y0, X1Y1, C10, S11, C11);

fulladd s12(X3Y0, X2Y2, C11, S12, C12);

halfadd s13(X3Y3, C12, S13, C13);

logic C10, C11, C12, C13;

logic S20, S21, S22, S23;

halfadd s20(S11, X0Y2, S20, C20);

fulladd s21(s12, X1Y2, C20, S21, C21);

fulladd s22(S13, X2Y2, C21, S22, C22);

fulladd s23(X3Y2, C13, C22, S23, C23);

logic C20, C21, C22, C23;

logic S30, S31, S32, S33;

halfadd s30(S21, X0Y1, S30, C30);

fulladd s31(s22, X2Y3, C30, S31, C31);

fulladd s32(S23, X2Y3, C31, S32, C32);

fulladd s33(X3Y3, C23, C32, S33, C33);

logic C30, C31, C32, C33;

assign X0Y0 = X[0] & Y[0];

assign P[0] = X0Y0;

// Write your code for P[1] - P[6]

// assign X1Y0 = X[1] & Y[0];

// assign X1Y0 = X[0] & Y[1];

// halfadd ha1(X1Y0, X0Y1, S10, C10);

assign P[1] = S10;

assign P[2] = S20;

assign P[3] = S30;

assign P[4] = S11;

assign P[5] = S12;

assign P[6] = S13;

assign P[7] = C33; //check once only this

endmodule

/* ECE 37100: Lab 3 32-bit ALU that can perform ADD, SUB, AND, and ORR operation inputs: A -> 32-bit, B -> 32-bit, ALUControl -> 2-bit outputs: Result -> 32-bit, ALUFlags -> 4-bit */ module alu(input logic[31:0] A, B, input logic[1:0] ALUControl, output logic[31:0] Result, output logic[3:0] ALUFlags); reg [32:0] Carry; // Use always_comb always_comb begin case(ALUControl) 2'b00: {Result, Carry} = a + b; //addition // Overflow Flag // ALUFlags[0] = (~(a[31]^b[31])^Result[31]) // Carry Out Flag // ALUFlags[1] = ((Carry[32] == 1) ? 1:0; 2'b01: Result = a - b; //subtraction // Overflow Flag // ALUFlags[0] = (~(a[31]^b[31])^Result[31]) // Carry Out Flag // ALUFlags[1] = ((Carry[32] == 1) ? 1:0; 2'b10: Result = a & b; 2'b11: Result = a I b; endcase assign neg = Result[31]; assign zero = (Result == 32'b0); assign carry = (ALUControl[1] == 1'b0) & sum[32]; assign overflow = (ALUControl[1] == 1'b0) & ~(a[31] ^ b[31] ^ ALUControl[0]) & (a[31] ^ sum[31]); assign ALUFlags = {neg, zero, carry, overflow}; // zero flag ALUFlags[2] = (Result == 32'b0) ? 1:0; // Negative Flag AlUFlags[3] = (Result[31]) ? 1:0; // Put multiple statements inside begin-end block end endmodule module alu_tb(); logic[31:0] A, B, Result; logic[1:0] ALUControl; logic[3:0] ALUFlags; // instantiate device under test alu dut(A, B, ALUControl, Result, ALUFlags); // apply inputs one at a time initial begin A = 32'h00000000; B = 32'h00000000; ALUControl = 2'b00; #10; assert(Result === 32'h00000000 & ALUFlags === 4'b0100) $display("Test A=%h, B=%h, ALUControl=%b passed", A, B, ALUControl); else $error("Test A=%h, B=%h, ALUControl=%b failed", A, B, ALUControl); // Provide other test cases from the table // Instantiate the Unit Under Test (UUT) alu uut ( .a(a), .b(b), .ALUControl(ALUControl), .Result(Result), .ALUFlags(ALUFlags) ); initial begin // Initialize Inputs $monitor("time = %0d a = %0d, b = %0d, ALUControl = %0d, Result = %0d, ALUFlags = %4b", $time, a, b, ALUControl, Result, ALUFlags); a = 32'd23; b = 32'd44; ALUControl = 2'd0; #10; ALUControl = 2'd1; #10; ALUControl = 2'd2; #10; ALUControl = 2'd3; #10; a = 32'd98; b = 32'd144; ALUControl = 2'd0; #10; ALUControl = 2'd1; #10; ALUControl = 2'd2; #10; ALUControl = 2'd3; #10; a = 32'd127; b = 32'd187; ALUControl = 2'd0; #10; ALUControl = 2'd1; #10; ALUControl = 2'd2; #10; ALUControl = 2'd3; #10; a = 32'd156; b = 32'd109; ALUControl = 2'd0; #10; ALUControl = 2'd1; #10; ALUControl = 2'd2; #10; ALUControl = 2'd3; #10; end endmodule ************** Output of the Program ***************** time = 0 a = 23, b = 44, ALUControl = 0, Result = x, ALUFlags = xx00 time = 10 a = 23, b = 44, ALUControl = 1, Result = x, ALUFlags = xx00 time = 20 a = 23, b = 44, ALUControl = 2, Result = 4, ALUFlags = 0000 time = 30 a = 23, b = 44, ALUControl = 3, Result = 63, ALUFlags = 0000 time = 40 a = 98, b = 144, ALUControl = 0, Result = 63, ALUFlags = 0000 time = 50 a = 98, b = 144, ALUControl = 1, Result = 63, ALUFlags = 0000 time = 60 a = 98, b = 144, ALUControl = 2, Result = 0, ALUFlags = 0100 time = 70 a = 98, b = 144, ALUControl = 3, Result = 242, ALUFlags = 0000 time = 80 a = 127, b = 187, ALUControl = 0, Result = 242, ALUFlags = 0000 time = 90 a = 127, b = 187, ALUControl = 1, Result = 242, ALUFlags = 0000 time = 100 a = 127, b = 187, ALUControl = 2, Result = 59, ALUFlags = 0000 time = 110 a = 127, b = 187, ALUControl = 3, Result = 255, ALUFlags = 0000 time = 120 a = 156, b = 109, ALUControl = 0, Result = 255, ALUFlags = 0000 time = 130 a = 156, b = 109, ALUControl = 1, Result = 255, ALUFlags = 0010 time = 140 a = 156, b = 109, ALUControl = 2, Result = 12, ALUFlags = 0000 time = 150 a = 156, b = 109, ALUControl = 3, Result = 253, ALUFlags = 0000

Questions:

Lab Assignment 3, Total Points: 25 Objectives Able to use structural modeling to implement complex circuits. Able to use always_comb, case, and if-else statements in SystemVerilog. Able to write a testbench for simulation. Tasks Task 1 [10 points]. An array multiplier is a parallel multiplier that generates the partial products in a parallel fashion. The various products are added as soon as they are available. Two N-bit unsigned numbers X and Y are multiplied to generate a product that is possibly 2N bits. Figure 1 shows two 4-bit unsigned numbers X and Y multiplication. In general, an N- bit multiplier would require N2 AND gates, N*(N-2) full adder, and N half-adder. Half adder: A half adder has two inputs, A and B, and two outputs, S and Cout. S is the sum of A and B. Cout holds the carry out of the sum. The half adder can be built from an XOR gate and an AND gate. Full adder: A full adder has three inputs, A, B, and Cin along with two outputs, S and Cout. S is the sum of A, B, and Cin. Cout holds the carry out of the sum. Figure 1: 4-bit array multiplier Figure 2: Half adder Figure 3: Full-adderUse the arrmul.sv file as a template to implement a 4x4-array multiplier module arrmul. Perform the following activities to complete the task: 1. Create a new Quartus Prime project using File -> New -> New Quartus Prime Project with the following attributes: a. Project Directory: lab3 b. Project Name: lab3 c. Top-level Entity: arrmul 2. Add the template file arrmul.sv in the project using Project -> Add/Remove files in project. Browse the arrmul.sv file and add it into the project. Set this file as top-level entity. 3. Complete the arrmul.sv file. 4. Perform Analysis & Synthesis using Processing -> Start -> Analysis & Synthesis. 5. The compilation should take place without errors and warnings. If you find any error or warnings, then fix it. 6. Create a University Program VWF using File -> New -> University Program VWF. Configure the file with the following specification: a. Insert all signal nodes/buses using Edit -> Insert -> Insert Node or Bus -> Node Finder -> List. Then add all the nodes in Nodes found to Selected Nodes by pressing the >> button. b. Set the simulation end time to 10ns using Edit -> Set End Time. c. Set the grid size to 1ns using Edit -> Grid Size. d. Use the Random values button to configure input signals to cycle through random logic bus values throughout the simulation. e. Start functional simulation using Simulation -> Run Functional Simulation and verify whether outputs are getting the correct values. Deliverables 1. [5 points] Code screenshot of arrmul.sv file and upload the file separately. 2. [1 points] Screenshot of successful compilation of arrmul module. 3. [3 points] Screenshot of simulation result for the module. 4. [1 points] Screenshot of RTL Viewer of the module. Task 2 [15 points]. An Arithmetic and Logical Unit (ALU) is an important hardware in processors datapath. It is used to perform arithmetic and logical operations, such as add, subtract, logical AND, and logic OR. In this task, you will create a 32-bit ALU SystemVerilog module, using the given alu.sv with the following module declaration: module alu (input logic[31:0] a, b, input logic[1:0] ALUControl, output logic[31:0] Result, output logic[3:0] ALUFlags); In the module, a and b are operands to the ALU. ALUControl determines the operation to be performed. Assume 00, 01, 10, and 11 for add, subtract, logical AND, and logical ORoperations, respectively. The four bits of ALUFlags should be set to 1 if the given condition in the below table is met. ALUFlag bit Meaning Bit 3 (N) Result is negative Bit 2 (Z) Result is 0 Bit 1 (C) The adder produces a carry out Bit 0 (V) The adder results in overflow SystemVerilog Testbench: Before writing the testbench, fill the missing cells in ALUControl, B, Result, and ALUFlags columns in Table 1. Now, write a testbench that takes ALU inputs from columns ALUControl, A, and B; and generates Result and ALUFlags. The produced outputs should be similar to Result and ALUFlags. Remember that each hexadecimal digit in the table represents 4 bits. Be careful when pulling signals from the file that are not multiples of four bits. Table 1: ALU Testbench Test ALUControl A B Result ALUFlags ADD 0+0 0 00000000 00000000 00000000 4 (0100) ADD 0+(-1) 0 00000000 FFFFFFFF FFFFFFFF 8 (1000) ADD 1+(-1) 0 00000001 FFFFFFFF 00000000 6 (0110) ADD FF+1 0 000000FF 00000001 SUB 0-0 1 00000000 00000000 00000000 SUB 0-(-1) 00000000 FFFFFFFF 00000001 SUB 1-1 00000001 SUB 100-1 00000100 AND FFFFFFFF, FFFFFFFF FFFFFFFF AND FFFFFFFF, 12345678 FFFFFFFF 12345678 12345678 AND 12345678, 87654321 12345678 AND 00000000, FFFFFFFF 00000000 OR FFFFFFFF, FFFFFFFF FFFFFFFF OR 12345678, 87654321 12345678 OR 00000000, FFFFFFFF 00000000 OR 00000000, 00000000 00000000 Perform the following tasks to complete the module: 1. Complete Table 1 for the testbench module. 2. Add the template file alu.sv in the project created in Task 1 using Project -> Add/Remove files in project. Browse the alu.sv file and add it into the project. Set this file as top-level entity. 3. Complete the alu.sv file for alu and alu_tb modules. Use Table 1 for completing alu_tb module. 4. Perform Analysis & Synthesis using Processing -> Start -> Analysis & Synthesis.5. The compilation should take place without errors and warnings. If you find any error or warnings, then fix it. 6. In Tools -> Options -> General -> EDA Tools, provide the path for win32aloem in ModelSim and ModelSim-Altera. 7. To simulate the testbench, start ModelSim using Tools -> Run Simulation Tool -> RTL Simulation 8. In ModelSim, expand work from Library pane and click alu_tb then select all the signals from Objects pane and add them for simulation using Add Wave. 9. Then go to Simulate -> Run -> Run All. It will simulate the testbench. Verify that you get the correct simulation results. If yes, then take the screenshots for simulation waveform and Transcript windows. Deliverables 1. [4 points] Complete table for the testbench. 2. [6 points] Code screenshot of alu.sv file for alu and alu_tb modules and upload the file separately. 3. [1 points] Screenshot of successful compilation of alu module. 4. [3 points] Screenshot of simulation waveform and Transcript windows. 5. [1 points] Screenshot of RTL Viewer of the module.