Need the Verilog code if possible

Design and simulate a digital circuit that can be attached to school bill, which can work from 8:00 AM to 12:50 PM, and it has the following features: 1- Rings for 10 seconds. 2- Start ringing 8:00 AM to announce for the field gathering. 3- Rings 8:40 for going to class. 4- Rings for the start of the first class period at 8:50 AM. 5- Rings for end of each period after 40 minutes from its start. 6- Rings for break after 10 minutes from the end of the previous period to announce for the next class period. Assume a clock of period 20 seconds shown below available to you to be connected to the clock line of the circuit. Iz 20 seconds Assume an enable line of value 1 at 8:00 AM and value 0 at 12:55 PM Design and simulate a digital circuit that can be attached to school bill, which can work from 8:00 AM to 12:50 PM, and it has the following features: 1- Rings for 10 seconds. 2- Start ringing 8:00 AM to announce for the field gathering. 3- Rings 8:40 for going to class. 4- Rings for the start of the first class period at 8:50 AM. 5- Rings for end of each period after 40 minutes from its start. 6- Rings for break after 10 minutes from the end of the previous period to announce for the next class period. Assume a clock of period 20 seconds shown below available to you to be connected to the clock line of the circuit. Iz 20 seconds Assume an enable line of value 1 at 8:00 AM and value 0 at 12:55 PM