Note: Falling-edge is the change from 1 to 0. ClrN and PreN are the negative logic type. Asynchronous pre and clr (a) Complete the following timing diagram for a J-K flip-flop with a falling-edge 1. trigger and asynchronous ClrN and PreN inputs. ClrN PreN Clock (b) Complete the timing diagram for the following circuit. Note that the Ck inputs on the two flip-flops are different. ClrN Clock CLR ClrN Ck D Q1 Clock