NOTE: Submit the completed project folder by the due date specified on blackboard. The project name must follow this format: fistlast-Project2.zip. Thoroughly comment your code and the testbench file. The first comments to appear in all o your code files must be the following: /* Name: First Last names R-Number: R-XXXX... Assignment: Project X / Replace the highlighted parts with the relevant information. Write Verilog code to create a 3232 register file. The register file should have two output busses (bus A and bus B ), along with their corresponding bus addressing lines for each bus. The register file must allow loading the registers one at a time through an input data bus (Bus "D"), bus D address lines (DA), and register load signal (RL). Provide a working test bench as proof that your project is working. Test all registers for read (bus A and B) and write capability