Now, back to the problem. Let's consider a 1GiB cycle stealing data transfer. Thus, for each word of this 1GiB, the DMAC must request, and the DPU must grant permission. We have two basic questions. - How long does this transfer take, including the grant/request overhead? This is relatively easy to answer. - During the transfer, by what percentage is the CPU slowed down? This is harder to answer We want to compare how many instructions the CPU would have executed without the data transfer during that time and how many it does with the data transfer. Assumptions: - The device transmits data at 10MiB per second, and the memory bus can handle this bandwidth. - We will assume that instruction fetches can be ignored, i.e., that instructions are fetched without any delay to the CPU, due to a high instruction cache hit rate, along with branch prediction and other architecturations - The CPU executes 1 billion one-word-long instructions per second (i.e., 1GHz ). However, this does not include any slowdown necessary for accessing cache or memory, e.g., for load and store operations. To understand that slowdown, we have the following. - We avoid all memory bus contention between the CPU and DMAC. More specifically, we assume that the CPU can avoid stalls waiting for memory access during times that memory access has been granted to the DMAC, and all CPU accesses to memory are complete before the DMAC gets control of the memory bus. - On average, 10% of instructions have data operands in memory. - The data cache hit rate is 95%. - Data cache hits are serviced within the same cycle, not delaying the CPU. - A data cache miss makes the instruction take 10 times as long. - Each bus request and grant requires 100 instructions, none of which access memory. Finally, we restate the overall program in several parts. a. (5 points) How long does this data transfer take with cycle stealing? b. (10 points) How many program instructions would have been executed during that time, assuming no data transfer? c. (5 points) How many program instructions are executed during that time with the data transfer