Num$1=$ DB $(=11011011)$

Num$2=$ AE $(=10101110)$

a$)$ Pick $6$ and $7$th bits of num$110$

b$)$ Replicate $2$ times $1010$

c$)$ Pick first three bits of num $1011$

d$)$ Pick first $4$ bits of num$21110$

e$)$ Concatenate d$,$c$,$ and b $->[11100111010]$

f$)$ Divide concatenated number by constant $110010$

g$)$ Verilog module $($dataflow$),$ RTL scheme, Testbench, Simulation

Result $\backslash (=100101=\backslash )$ h$25$