number 5

Your answer should be a system Verilog module code and a screen capture showing the number of errors and warnings, there should be no errors 5) Write a Register File Module. It should be sequential and not contain inferred latches. To show that it doesn't have inferred latches compile in Quartus prime and capture the number of errors and warnings. Be sure to use System Verilog. Your answer should be a system Verilog module code and a screen capture showing the number of errors and warnings, there should be no errors. Images as always should be in pdf form