Objective: Design a Non$-$binary Counter using D Flip$-$Flops that counts $0,1,2,4,5,6,0,....$

Steps:

A$)$ Construct the State Table. Consider unused states as don't care conditions.

The State Table should include the Present State, Next State, and inputs to D Flip$-$Flops.

B$)$ Using K$-$maps find the simplified input equations $($combinational circuits$)$ to the D Flip$-$Flops.

C$)$ Draw the complete logic circuit diagram including the D Flip$-$Flops, but

without the $7-$segment display.

D$)$ Using Logic.ly simulate and verify the circuit works. Use the $7-$segment

display to display the output as a decimal digit, i$.$e$.0,1,2,4,5,6,0,$dots

What to turn in:

You need to turn in a report as a single pdf that will contain the following:

A title page with the following information:

a$)$ Class: CSE $3100$ Digital Logic

b$)$ Your Name

c$)$ Lab $8$: Design a Non$-$binary Counter using D Flip$-$Flops that counts $0,1,2,$

$4,5,6,0,$dots

The State Table

The K$-$maps with simplified logic circuits $($on paper, not in Logic.ly$).$

The complete Logic circuit diagram including the D Flip$-$Flops drawn on paper.

A screenshot from Logic.ly that contains the complete circuit implementation

including the $7-$segment display.

Write the output sequence of the $7-$segment display you observe in Logic.ly$.$