Objective:

To implement a Verilog gate level model for $32-$bit basic logic gates.

Outcome:

Gate level implementation for the following components.

NOR$32\_2$x$1$

AND$32\_2$x$1$

INV$32\_1$x$1$

OR$32\_2$x$1$

Instruction:

Download HDL source code from prj$\_03.$zip Download prj$\_03.$zip, unzip and copy content into directory CS$147-$Project$03$

Create a Verilog project as Project$03$

Include all $*.$v files form directory CS$147-$Project$03$

Include all $*.$v files from directory CS$147-$Project$03/$TESTBENCH

Complete gate level description of following components in logic$\_32\_$bit.v

NOR$32\_2$x$1$

AND$32\_2$x$1$

INV$32\_1$x$1$

OR$32\_2$x$1$

Compile entire Project$03$ and simulate following modules in ModelSim simulator.

NOR$32\_2$x$1\_$TB

AND$32\_2$x$1\_$TB

INV$32\_1$x$1\_$TB

OR$32\_2$x$1\_$TB

Observe corresponding outcomes on waveform windows and fix any issue.

Each testbench will generate corresponding output file.

OUTPUT$/$NOR$32\_2$x$1\_$TB$.$out

OUTPUT$/$AND$32\_2$x$1\_$TB$.$out

OUTPUT$/$INV$32\_1$x$1\_$TB$.$out

OUTPUT$/$OR$32\_2$x$1\_$TB$.$out

This should match with corresponding golden output file CS$147-$Project$03/$GOLDEN$/$ directory.

NOR$32\_2$x$1\_$TB$.$out.golden

AND$32\_2$x$1\_$TB$.$out.golden

INV$32\_1$x$1\_$TB$.$out.golden

OR$32\_2$x$1\_$TB$.$out.golden

Add more testing in these testbenches to make sure outcome is correct.

Submission

Archive current CS$147-$Project$03$ directory into CS$147-$Project$03-$LA$02.$zip.

Upload CS$147-$Project$03-$LA$02.$zip into assignment submission in Canvas.

Make sure you have uploaded correct file.

Download CS$147-$Project$03-$LA$02.$zip into a separate directory.

Recreate corresponding project in ModelSim and simulate assignment to regenerate output and compare.