On Architecture A$,$ how many clock cycles does it take from the fetch of the $\text{'}$Iw$\text{'}$ all instructions have reached the $\text{'}W\text{'}$ stage? Use of $\text{'}F\text{'}$ registers indicate floating point.

$lw.DF3,O(R2)$

mul.$DF4,F5,F2$

add.$DF6,F8,F7$

$sw.DF9,0(R2)$

$\backslash$table$[[,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,],[,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,]]$

On Architecture A$,$ how many cycles does it take from the fetch of the $\text{'}$lw$\text{'}$ all instructions have reached the $\text{'}W\text{'}$ stage?

Iw$.$D F$3,0($R$2)$

mul.D F$4,$ F$3,$ F$2$

add.D F$6,$ F$4,$ F$7$

sw$.$D F$6,0($R$2)$

$\backslash$table$[[,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,],[,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,]]$