On startup we look at first detecting the sequences either $101$ or $010($just one of them$).$

After one of the leading sequences $(101$ or $010)$ is detected we ignore subsequent instances of such

sequences and then look to detect the sequence $111.$

After the sequence $111$ is detected once, we ignore subsequent instances of $111\text{'}$s$,101$ and $010$ and look

to detect the sequence $000.$ After such sequence has been detected we start the process all over again by

detecting either $101$ or $010.$ The process continues repeating itself by again detecting once the $111$

sequence and then once the $000$ sequence. The cycle continues.

The timing trace shown below depicts a possible example, using Moore, depicting some detections

events in order to clarify the prescribed functionality for this FSM$.$

If possible, provide alternative design solutions stating any trade$-$offs among them.

Use LogiSim to verify, and demonstrate to the instructor, that your design works as intended.

Provide a full state diagram and follow the procedure given in class to synthetize a logic circuit.

I am mainly interested in the LogiSim design