Question: OPCODE specifies the OPeration's CODE. DST specifies a DeSTination register. SRC specifies a SouRCe register. IMM specifies a 2 ' s complement value ( that

OPCODE specifies the OPeration's CODE.
DST specifies a DeSTination register.
SRC specifies a SouRCe register.
IMM specifies a 2's complement value (that's IMMediately available as part of the instruction).
Assume the architecture has 32-bit instructions, 242 opcodes, and 64 registers.

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