or$-4480C$ ar$6$o $4$

Problem $2.(12$ points$)$ Basic cache

Consider the following $C$ code.

Assume the above code is executed on a machine with the following conditions:

sizeof$($int$)=4.$

The array src starts at address $0$ and the array dst starts at address $040($i$.$e$.,$ decimal $64).$

The machine has a direct$-$mapped L$1$ data cache with $16-$byte blocks with write$-$back, writeallocate policy. The cache capacity is $32$ bytes $($i$.$e$.,$ two c$$che blocks$)$ and is initially empty.

$12-$ Memory accesses to the array src and$$st are the only sources of data cache accesses $($i$.$e$.,$ all other variables reside in registers$).$

The array is stored in the memory in row$-$major order.

$16$

$50$

$44$

$($A$)(8$ points$)$ For access of each array element in the table below, indicate whether it resulted in ache hit or miss by writing $"h"$ for a hit and $"m"$ for a miss. What is the cache miss rate? $($D$)$ aw the table on

exam.net$)$

$16\mathrm{.}20,2$

$36$

$\backslash$table$[[,$dst$\mathrm{.}0,$Col$\mathrm{.}1,$col$\mathrm{.}2,$col$\mathrm{.}3],[$Row$0,M,N,N,N$