P1. (24 points) a) Design a 3-bit counter that counts in the sequence 0,1,2,3,4,5,6,7,0,1, This counter counts if its enable input w is equal to 1, otherwise it does not increment its count. If its zero input z is equal to 1, the state resets to 0 in the next cycle otherwise normal counting behavior occurs (i.e., z has higher priority than w). Use D flip-flops and include the state diagram, state-assigned table, next-state expressions and minimized SOP output expressions all clearly labeled. Let y2, y1, and y0 be the current state values.

b) Using your result from part (a), design a modulo-6 counter that counts in the sequence 0, 1, 2, 3, 4, 5, 0, 1,

c) Modify part (a) to count in the following sequence 1,2,3,4,1,2,.... (the counter zeros to 1 now). Work through the entire design process and include updated state diagram, state-assignment table, etc. Make sure to minimize the number of flipflops.