Part 1 1) Design a combinational circuit with three inputs, x, y and z , and three outputs, A, B, C . When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6, or 7, the binary output is two less than the input. 2) A majority circuit is a combinational circuit whose output is equal to 1 if the input variables have more 1s than 0s. The output is 0 otherwise. Design a 3-input majority circuit by finding the circuits truth table, Boolean equation, and a logic diagram. 3) Design a BCD-to-decimal decoder using the unused combinations of the BCD code as dont-care conditions. 4) Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-to-4-line decoder. 5) Using a decoder and external gates, design the combinational circuits defined by the following five Boolean functions: a) F1 = x'yz' + xz b) F2 = (y' + x)z c) F3 = xy'z' + x'y d) F4 = y'z' + x'y + yz' e) F5 = x'y'z' + xy

Part 2 1) Create a new project as explained in your first homework. 2) Design a circuit, COMP_1_bit, for comparing two 1-bit positive integers, a and b. The outputs are x, y, z as defined below: a>b x=1, y=0, z=0 a=b x=0, y=1, z=0 aB, then X=1, Y=0, Z=0 A=B, then X=0, Y=1, Z=0 A

c) Produce the RTL schematic of your design. d) Write a VHDL code for a CON_COMP_1_bit by using COMP_1_bit and CONNECT as building blocks. Save this file by giving name as CON_COMP_1_bit.vhd. e) Add your COMP_1_bit.vhd by Add Sources, Add or create design sources to your project. f) Write a VHDL code for POZ_COMPARE by using COMP_1_bit and CON_COMP_1_bit as building blocks. Save this file by giving name as POZ_COMPARE.vhd g) Add your POZ_COMPARE.vhd by Add Sources, Add or create design sources to your project. h) Produce the RTL schematic of your design. i) Write a test bench file with name POZ_COMPARE_tb.vhd to test your design. j) Add your POZ_COMPARE_tb.vhd by Add Sources, Add or create simulation sources to your project. k) Simulate your design.