PART 1 - Design a state machine solution for the state diagram in Figure 5-1. Use D flip-flops and only equations (assign statements) to implement this design. (No "if else" OR "case" statements can be used here, [just for RESET]). Use K-maps to find the equations for each of the inputs to the D flip-flops. Implement your equations from the K-maps into Verilog code, and bring your Verilog file to lab. Compile your file and assign pins, download and test your solution. Since this type of state machine has an "implied" system clock you will have to provide a clock for your testing. Monitor the outputs of your state machine. You will have four types of outputs: the present state of the flip-flops, the Next State logic outputs for the D-F/Fs the Moore output and the Mealy output. These should all be assigned to LEDs. ~X/~Y ~X/Y SO W=0 S4, S5, S6 W=1 X/Y X/~Y ~X/~Y Reset = 0 Figure 5-1: State Diagram S2 W=1 X/Y S7 W=0 ~X/Y ~X/~Y X/Y S3 W=1 ~X/Y X/Y X-INPUT Y- Mealy OUTPUT W - Moore OUTPUT S1 W=0 X/~Y