Question: ( Part 3 ) Suppose the transmitting UART has a clock that is running 2 % faster than the receiving UART. Given that the receiver

(Part 3) Suppose the transmitting UART has a clock that is running 2% faster than the receiving UART. Given that the receiver oversamples each bit 16 times, how many incorrect samples could occur due to this clock mismatch over the course of 10 bits (1 start bit, 8 data bits, and 1 stop bit)? Would the receiver still be able to correctly sample the bits?

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