Part A: 3 marks The table below shows the state of the cache at time to. The most recent four memory accesses, in order from least recent to most recent, have been: O Write Ox5435 Write Ox3329 Write Ox4AB1 Read OxOFEF . Fill in the boxes in the table. If you do not know the state of a bit, give it value X. Tag Dirty (Y/N) Replace (Y/N) Line 0 1 Data Ox5430-0x5437 Ox4ABO-OX4AB7 Ox3328-0x332F OxOFE8-OxOFEF 2 3 Part B: 3 marks The next access to take place is a read to address 0x1234. Show how the cache looks after this read. If a word transfer between memory and cache requires 4 clock cycles and a transfer between memory and CPU requires 1 clock cycle, how many clock cycles were required for this read? Line Tag Data Dirty (Y/N) Replace(Y/N)