Part A: Single Cycle Processor

Run the given Lab$2.$asm file on MARS simulator. Using the Tools$->$MIPS X Ray, you would be able to see the datapaths of the instructions. Based on the above figure, what will be the values of the followings when the following instructions are executed:

Hint:

Identify the instruction during the specified cycle.

Identify the datapath of the identified instruction, then determine the values of the labels for that datapath.

The datapath follows the instruction class datapath, i$.$e$.,\frac{R}{\text{I}}\frac{?}{?}\frac{J}{l}oa\frac{d}{?}$ store.

If the datapath does not cross through the label, mark it as $\text{'}x\text{'}.\backslash$table$[[$No$.,$Label,Value during cycle $5,$Value during cycle $7],[1,$a$,,],[2,$b$,,],[3,$c$,,],[4,$d$,,],[5,$e$,,],[6,$f$,,],[7,$g$,,],[8,$h$,,],[9,$i$,,],[10,$j$,,],[11,$k$,,],[12,$m$,,],[13,$n$,,],[14,$p$,,],[15,$q$,,],[16,$r$,,],[17,$s$,,],[18,$RegDst,,$],[19,$Branch,,$],[20,$MemRead,,$],[21,$MemtoReg,,$],[22,$ALUOp,,$],[23,$MemWrite,,$],[24,$ALUSrc,,$],[25,$RegWr,,$],[26,$PCSrc$,,],[27,$Zero,,$]]$ Part B: Multi Cycle Processor

Copy the multicycle processor datapath $($Figure B$),$ so there are $2$ datapath figures.

For each figure, assuming Lab$2.$asm runs on the multicycle processor, draw the datapath AND write the values of the control signals for the following instructions:

a$.$ Figure $1.$ Process in cycle $19.$

b$.$ Figure $2.$ Process in cycle $33.$

Make sure to:

a$.$ label the instruction for each figure.

b$.$ write the corresponding RTL statement$($s$)$ for the instruction during the cycle based on Table $1.$

c$.$ write the control values next to the labels in the figure $($the name of the control signal $-$ do NOT write the control values in a separate table$).$ There are altogether $12$ control values. For the Operation, just write the ALU operation, e$.$g$.$ ADD, SUB, etc. $-$ not in the format of bit value.

Make sure the file format to submit is a PDF file only $($ONE file only$).$

IRWrite

Hint:

Identify the instruction and the specific process during the specified cycle.

Identify the relevant RTL statements, and the datapath of the identified instruction$/$process$.$

The datapath follows the instruction class datapath, i$.$e$.,$ R$/$I$/$J$/$load$/$storeTable $1$: RTL statements

$\backslash$table$[[$Step name,$\backslash$table$[[$Action for R$-$type$],[$instructions$]],\backslash$table$[[$Action for memory$-$reference$],[$instructions$]],\backslash$table$[[$Action for$],[$branches$]],\backslash$table$[[$Action for$],[$jumps$]]],[$Instruction fetch,$\backslash$table$[[$IR$=$ Memory PC$],[$PC$=$PC$+4]]],[\backslash$table$[[$Instruction$],[$decode$/$register fetch$]],)],[\backslash$table$[[$Execution$,$ address$],[$computation$,$ branch$/],[$jump completion$]],$ALUOut $=$ A op B$,\backslash$table$[[$ALUOut $=$ A $+$ sign$-$extend$],[($IR$[15-0])]],\backslash$table$[[$if $($A$==$B$)$ then$],[$PC$=$ALUOut$]],\backslash$table$[[$PC$=$PC$[31-28]||],[($IRtable$[[$Memory access or R$-$type$],[$completion$]],\backslash$table$[[$Reg$[$ IR$[15-11]]=],[$ALUOut$]],\backslash$table$[[$Load: MDR $=$ Memory$[$ALUOut$]],[$or$],[$Store: Memory $[$ALUOut$]=$ B$]],,],[$Memory read completion,,Load: Reg$[[$R$[20-16]]=$ MDR$,,]]$Lab $2$Table $1$: RTL statements

$\backslash$table$[[$Step name,$\backslash$table$[[$Action for R$-$type$],[$instructions$]],\backslash$table$[[$Action for memory$-$reference$],[$instructions$]],\backslash$table$[[$Action for$],[$branches$]],\backslash$table$[[$Action for$],[$jumps$]]],[,\backslash$table$[[$IR$=$ Memory PC$],[$PC$=$PC$+4]]],[\backslash$table$[[$Instruction$],[$decode$/$register fetch$]],],[\backslash$table$[[$Execution$,$ address$],[$computation$,$ branch$/],[$jump completion$]],$ALUOut $=$ A op B$,\backslash$table$[[$ALUOut $=$A$+$ sign$-$extend$],[($ IR $[15-0])]],\backslash$table$[[$if $($A$==$B$)$ then$],[$PC$=$ALUOut$]],\backslash$table$[[$PC$=$PC$[31-28]$ II$],[($IRtable$[[$Memory access or R$-$type$],[$completion$]],\backslash$table$[[$Reg$[$ IR $[15-11]]=],[$ALUOut$]],\backslash$table$[[$Load: MDR $=$ Memory$[$ALUOut$]],[$or$],[$Store: Memory $[$ALUOut$]=$ B$]],,],[$Memory read completion,,Load: Reg$[$IR$[20-16]]=$ MDR$,,]]$

$\backslash$table$[[$Lab$2.$asm,$],[1,$#Lab $2],[2,.$ data$],[3,$arrayone: $.$byte $0$xaa, $0$x$22,0$xbb$,0$x$44],[4,,],[5,$text$],[6,1$i$,$$s$2,0\backslash$times $3344],[7,1$i$,$$s$3,0\backslash$times $55],[8,$la$,$$s$5,$ arrayone$],[9,$xori,$s$1,$$s$2,0$xaa$55],[10,$and,$s$4,$$s$1,$$s$3],[11,1$b$,$$t$1,2($$s$5)]$

Processor design plays a crucial role in the execution of instructions within a computer

system. The architecture of a processor determines how instructions are fetched, decoded,

executed, and written back to memory. Understanding different processor architectures is

essential for computer engineers, as it enables them to optimize performance, reduce power

consumption, and enhance overall system efficiency.

In this lab, we will explore the concepts of datapath and control signals in the context of both

Single Cycle and MultiCycle processors. Datapath refers to the path that data follows as it

moves through various components of the processor, such as registers, ALU, and memory.

Control signals, on the other hand, dictate the behavior of these components, coordinating

their operation to execute instructions correctly.

Our objective in this lab exercise is twofold. First, we aim to understand the underlying

principles of Single Cycle and MultiCycle Processor Designs, including their respective

datapaths and control signals. Second, we will apply this knowledge to identify the datapath

and control values for different MIPS instructions on both architectures.