Part II: Modifying the Counter for additional functionality.

In this section we will add some additional functionality to the counter.

$1.)$ Our first task will be adding a clock$-$enable to the counter. Add an input pin to the bdf called CE

Implement clock$-$enable using only FOUR $2-$input gates.

HINT: look at the following state table for clock enable to determine how best to implement it$.$

TFF state table:

Template Question: Wire the TFF below so that it matches the table.

$2.)$ Test your design by reproducing the screenshot below. Notice how the counter pauses while CE is low.

end time: $200n,$ grid$-$size $10$ ns$,$ clock period $10ns,$ CE is low from $50$ns $-70$ns$.$

$3.)$ Now that we can pause our counter, let's add the ability to reset it synchronously. Note that this is

different form the asynchronous reset we already have. A synchronous reset will set the counter back

to $0000$ when selected but will do so on the next clock cycle.

To accomplish this, you will need FOUR $2$:$1$ mux chips. In Quartus this part is called $21$mux