Part II Write a VHDL Testbench that will test an 8 bit counter component counting to a specific value. You may use sample code from the textbook to generate your own 8 bit counter. Use the following parameters for your Testbecnh:

? Hold the reset high for 40ns after starting the test

? Create a clock that has a 50% duty cycle and a period of 20ns, that will feed the counter.

? Show the message: 30 reached when the count reaches 30.

? Stop the simulation after the count reaches 127 and display message: TEST PASSED.

? Show the timing diagram of the outputs generated by the component being tested (8 bits).

? Demonstrate your Testbench.

? Report any assumptions that you made in your report.

Now create a VHDL program that uses the 8 bit counter component that you created for the test bench. above. Use a clock with a period of 1 second to drive the counter. Use a push button switch to be the RESET for your counter, and another pushbutton switch to be the CLEAR. Demonstrate your VHDL program on the DE1 kit. Report any assumptions that you made in your report.