P=A'z'+Az=(A+z)'=(x+y+z)'

it is not( XOR )

1. Write a Verilog code to implement the parity generator function.
2. Simulate your circuit and show 4 testing cases.
3. Show your codes, simulation and testing cases in FPGA in your report.
4. Modify by adding in to the work in Task 1 to add parity detector circuit to the parity generator code.
5. Test the functionality on the FPGA. Add comments.
6. Simulate at least 2 cases with error and 2 cases with no error introduced.
7. Show your tables, codes, simulation results and pictures for testing cases in FPGA in your report for the communication system with error and without errors.
8. Dont forget to label each testing case.
9. How could the circuit in Task1 be modified to create an Even Parity generator?
10. How could the odd parity detector that you used in Task 2 be modified to create an Even Parity detector?
11. Could the even-parity detector detect the error in the transmission of following sequence? Why or why not?

12. Transmitted data: 0101 0011 Received data: 0100 001

screenshot graph and all codes plz