Question: Performance Modelling - RISC - V processor This project will require you to implement cycle - accurate simulators of a 3 2 - bit RISC
Performance Modelling RISCV processor
This project will require you to implement cycleaccurate simulators of a bit RISCV processor in C or
Python. The skeleton code for the assignment is given in file NYURVIcpp or
NYURVIpy
The simulators should take in two files as inputs: imem.text and dmem.txt files
The simulator should give out the following:
cycle by cycle state of the register file RFOutputtxt
Cycle by cycle microarchitectural state of the machine StateResulttxt
Resulting dmem data after the execution of the program DmemResulttxt
The imem.txt file is used to initialize the instruction memory and the dmem.txt file is used to initialize the
data memory of the processor. Each line in the files contain a byte of data on the instruction or the data
memory and both the instruction and data memory are byte addressable. This means that for a bit
processor, lines in the imem.txt file makes one instruction. Both instruction and data memory are in
"BigEndian" format the most significant byte is stored in the smallest address
The instructions to be supported by the processor are categorized into the following types:
The simulator should support the following set of instructions.
Tasks: Draw the schematic for a single stage processor and fill in your code in the to run the simulator. points Draw the schematic for a five stage pipelined processor and fill in your code to run the simulator. Theprocessor should be able ot take care of RAW and control hazards by stalling and forwarding. points Measure and report average CPI, Total execution cycles, and Instructions per cycle for both these coresby adding performance monitors to your code. Submit code and print results to console or a file.points Compare the results from both the single stage and the five stage pipelined processor implementationsand explain why one is better than the other. points What optimizations or features can be added to improve performance? Extra credit point
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