Pipeline Timing $(12$ points$)$ Suppose that a big chunk of combinational logic can be broken up into separate stages, labeled A to E$,$ with delays of $80ps,20ps,40ps,30ps$ and $65$ ps$.$ We already have one clocked register at the end of this combinational logic.

a$.(3$ pts$)$ Suppose that we want to increase throughput while only adding a single new pipeline register. Between what stages should the new register be added to maximize throughput?

b$.(4$ pts$)$ Suppose that we want to increase throughput while adding two new pipeline registers. Between what stages should the new registers be added to maximize throughput?

c$.(5$ pts $)$ Suppose that we want to increase throughput while adding three new pipeline