Pipelining can efficiently increase the performance of a processor by overlapping execution of instructions. However the efficiency of the pipelining depends upon how problems encountered during the implementation of pipelining are handled. These problems are known as hazards.

1. Given the following program:

LW R1, 0(R2) SUB R4, R2, R5 AND R6, R1, R4 OR R4, R1, R6

detect the hazards in the given program and propose two solutions for each hazard you detect.

2. Given the following program:

Add r1, r2, r3 Sub r4,r1,r3 And r6, r1, r7 Or r8, r1, r9 Xor r10, r1, r11

detect the hazards in the given program and propose two solutions for each hazard you detect. Show the timing of this instruction sequence for the RISC pipeline before and after the solution.