Pipelining. Given a cpu running at 300 MHz, assume there are no read competition between each stage of instruction completion Design uses a 4 stage fetch/execute and clock for each stage listed Opcode fetch 1 cycle, decode 1 cycle, Operand fetch - 3 cycles, execute 5 cycles Pay attention to CPU clock speed. And show units of A. Give the time in clock/cycles to execute 1 instruction. measurement. B. Give number of instructions per second if NON-pipelined C. Give number of instructions per second if pipelined. D. Give number of instructions per second if the e xecution step is super-scalar