Please answer all parts $($show all work$)$ and do not use any responses$/$solutons available on the site as they are incorrect. Use all attached images for extra info.

Below questions refer to a clock cycle in which the processor fetches the following instruction

word:

$10001110001100000000000000100000$

Assume that data memory is all zeros and that the processor$$s registers have the following

values at the beginning of the cycle in which the above instruction word is fetched:

a$)$ What is the output of the Sign$-$extend unit $(32$bits$)$ and the Input $1$ of MUX $2($output of

Jump Shift Left $2$ unit $($Jump address$[31-0],$ found in top left$))$ for this instruction word?

b$)$ What are the values of the ALU control unit$$s inputs for this instruction?

c$)$ What is the new PC address after this instruction is executed? Explain the path through

which this value is determined.

d$)$ For each MUX $($MUX $1$ to MUX $5),$ show the values of its data output during the

execution of this instruction and these register values.

e$)$ For the ALU and the two add units, what are their data input values?

f$)$ What are the values of all inputs $($both data and control signals$)$ for the $$Registers$$ unit? Question $3.(30$ Points$)$

Below questions refer to a clock cycle in which the processor fetches the following instruction

word:

$10001110001100000000000000100000$

Assume that data memory is all zeros and that the processor's registers have the following

values at the beginning of the cycle in which the above instruction word is fetched:

Answer the following by referring to Figure $1$ and information provided in Page $10,11$ and $12$:

a$)$ What is the output of the Sign$-$extend unit $(32$bits$)$ and the Input $1$ of MUX $2($output of

Jump Shift Left $2$ unit $($Jump address$[31-0],$ found in top left$))$ for this instruction word?

b$)$ What are the values of the ALU control unit's inputs for this instruction?

c$)$ What is the new PC address after this instruction is executed? Explain the path through

which this value is determined. d$)$ For each MUX $($MUX $1$ to MUX $5),$ show the values of its data output during the

execution of this instruction and these register values.

e$)$ For the ALU and the two add units, what are their data input values?

f$)$ What are the values of all inputs $($both data and control signals$)$ for the "Registers" unit? Figure $1.$ Single Cycle Implementation of MIPS Processor

Table $1.$ ALU and ALUop Control Signals$\backslash$table$[[$Op$(31$:$26)=01000($TLB$),$ rs$(25$:$21),,],[23-21,0(000),1(001),2(010),3(011),4(100),5(101),6(110),7(111)],[25-24,,,,,,,,],[0(00),$mfc$0,,$cfc$0,,$mtc$0,,$ctc$0,],[1(01),,,,,,,,],[2(10),,,,,,,,],[3(11),,,,,,,,]]$

$\backslash$table$[[$op$(31$:$26)=000000($R$-$format$),$ funct$(5$:$0)],[\backslash$table$[[2-0],[5-3]],0(000),1(001),2(010),3(011),4(100),5(101),6(110),7(111)],[0(000),\backslash$table$[[$shift left$],[$logical$]],,\backslash$table$[[$shift right$],[$logical$]],$sra,sllv$,,$srlv$,$srav$],[1(001),\backslash$table$[[$jump$],[$register$]],$jalr,,,syscall,break,,$],[2(010),$mfhi,mthi,mflo,mtlo,,,,$],[3(011),$mult,multu,div,divu,,,,$],[4(100),$add,addu,subtract,subu,and,or$,$xor,not or $($nor$)],[5(101),,,$set l$.$t$.,\backslash$table$[[$set I. t$.],[$unsigned$]],,,,],[6(110)],[7(111),,,,,,,,]]$

Table $4.$ MIPS Instruction Encoding