Please answer in detail.

) Consider a single core processor running at 2.0 GHz that can finish one instruction every 2 clock cycles on the average if the instructions and data are found in the L1 cache Consider an application where on the average, 20% of the memory acce instruction) miss out of L1 and go to L2, which requires 10 cycles of acces Furthermore, of the accesses going to L2, 20% again miss out and go to the memory, which has an average access time of 30 ns. sses (per a. Com pute the effective CPI for this application. Also, compute the execution time of the application if the path-length of the application is 1.5 billion instructions. Now suppose that you have an alternate design with larger L1 and smaller L2, so that the L1 miss rate is one-half (i.e., 10%) and L2 miss rate is double (i.e., 40%). Does this yield better performance than in (a)? Suppose in (a) we make the CPU twice as fast. By what percentage does the execution b. c. time go down? ) Consider a single core processor running at 2.0 GHz that can finish one instruction every 2 clock cycles on the average if the instructions and data are found in the L1 cache Consider an application where on the average, 20% of the memory acce instruction) miss out of L1 and go to L2, which requires 10 cycles of acces Furthermore, of the accesses going to L2, 20% again miss out and go to the memory, which has an average access time of 30 ns. sses (per a. Com pute the effective CPI for this application. Also, compute the execution time of the application if the path-length of the application is 1.5 billion instructions. Now suppose that you have an alternate design with larger L1 and smaller L2, so that the L1 miss rate is one-half (i.e., 10%) and L2 miss rate is double (i.e., 40%). Does this yield better performance than in (a)? Suppose in (a) we make the CPU twice as fast. By what percentage does the execution b. c. time go down