please answer in VHDL

6) Write a loop statement that samples a bit input d when a clock input clk changes to '1. So long as dis 'o', the loop continues executing. When d is '1', the loop exits. 6) Write a loop statement that samples a bit input d when a clock input clk changes to '1. So long as dis 'o', the loop continues executing. When d is '1', the loop exits