Question: Please answer parts d and e This is detailed question so just answer d and e A computer is being designed using a microprocessor with

 Please answer parts d and e This is detailed question so

Please answer parts d and e

This is detailed question so just answer d and e

A computer is being designed using a microprocessor with a 20-bit address bus (AO - A19). The 1MB address space is to be split and allocated to RAM, ROM and I/O hardware as follows: Address Range (hex) Contains Select Signal Ox20000-0x3FFFF RAM RAMCS Ox18000-Ox1FFFF I/O Area IOCS OxOC000-00FFFF External ROM EXTROMCS Ox00000-0x0BFFF 48KB Internal ROM ROMCS The rest of the address space is unused. Note: As with many computer systems, it its only necessary to decode the ad- dress to sufficiently identify each of the sections above uniquely. It is accept- able for some parts to be decodeable by more than one address provided these extra addresses do not overlap any of the other specified address ranges. Using a combination of AND, OR and NOT gates and the signals (A12- A19) that contain the top eight bits of the address in binary form: (a) Derive the equation for a logic signal, ROMCS, which is true if the address bus contains an address in the range for the 48KB Internal ROM. (b) Derive the equation for a logic signal, EXTROMCS, which is true if the address bus contains an address in the range for the External ROM. (c) Derive the equation for a logic signal, Iocs, which is true if the address bus contains an address in the range for I/O Area. (d) Derive the equation for a logic signal, RAMCS, which is true if the address bus contains an address in the range for RAM. (e) The design of the computer system is changed so that the RAM now runs from 0x20000-0x7FFFF. How would this change the equations needed for the four logic signals created above? What would the new logic equations be for ROMCS, EXTROMCS, IOCS and RAMCS? (0) A second, separate block of RAM is inserted into the address space at Ox80000 - OxFFFFF. (1) Derive the equation for a new logic signal, RAM2CS, which is true if the ad- dress bus contains an address in the range the new RAM block at Ox 80000. (ii) Which, if any, of your existing logic equations for ROMCS, EXTROMCS, IOCS, or RAMCS would need to be changed so that they still uniquely decode those areas of memory after the new block of RAM is added

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