please answer the quastions above withe explenation

1) A finite-state machine has 16 possible states. At each clock pulse, it reads in 3-bit input, and produce 4-bit output, and switches to a new state. a. what is the minimum # of binary varible needed to realize the states for the b. Drawa block diagram (notlogic design) of the abo sequential network, showing the interconnections ofinputs, outputs, and all internal states connections to/from the combinational block of this network. Assume that states are represented by D-F/F latch). How would you use a ROM (Read Only Memory) to realize this system. c. 2. Check the Micro-architecture given in class and indicate whether or not the two Mac statements below performs exactly the same function? Explain a) a,-a+a; if n then goto 0; and b) a-s|shift(a) if n then goto 0 3. Which of the following memories are possible? Which are reasonable? The answere could be PR (possible and reseanable), PU[possible and unreasonable), NP (not possible) a 10-bit address, 1024 cells, 8-bit cell size b 10-bit address, 1024 cells, 12-bit cell size c 9-bit address, 1024 cells, 10-bit cell size d 11-bit address, 1024 cells, 8-bit cell size e 10-bit address, 10 cells, 1024-bit cell size f 1024-bit address, 10 cells, 10-bit cell size 4. A 32 bit word computer employs 2 Gbytes of main memory and a cach of 2 Mega words. Determine the number of bits in each field of the address in the following organization: Set-associative map with a set size of four and a line size of 8 words Fully-assocoative map of 16 words. a. b. 5. Assume a 4-bit arithmatic pipeline which performs 4-bit fix point (integer) addition, realizing 1 bit ofaddition in each stage of pipeline process. Explain and show how this pipeline system can be modified to perform multiple of 4-bit computations (ike 8-bit, 12-bit, etc.) without increasing the stage (dept) of the pipeline 1) A finite-state machine has 16 possible states. At each clock pulse, it reads in 3-bit input, and produce 4-bit output, and switches to a new state. a. what is the minimum # of binary varible needed to realize the states for the b. Drawa block diagram (notlogic design) of the abo sequential network, showing the interconnections ofinputs, outputs, and all internal states connections to/from the combinational block of this network. Assume that states are represented by D-F/F latch). How would you use a ROM (Read Only Memory) to realize this system. c. 2. Check the Micro-architecture given in class and indicate whether or not the two Mac statements below performs exactly the same function? Explain a) a,-a+a; if n then goto 0; and b) a-s|shift(a) if n then goto 0 3. Which of the following memories are possible? Which are reasonable? The answere could be PR (possible and reseanable), PU[possible and unreasonable), NP (not possible) a 10-bit address, 1024 cells, 8-bit cell size b 10-bit address, 1024 cells, 12-bit cell size c 9-bit address, 1024 cells, 10-bit cell size d 11-bit address, 1024 cells, 8-bit cell size e 10-bit address, 10 cells, 1024-bit cell size f 1024-bit address, 10 cells, 10-bit cell size 4. A 32 bit word computer employs 2 Gbytes of main memory and a cach of 2 Mega words. Determine the number of bits in each field of the address in the following organization: Set-associative map with a set size of four and a line size of 8 words Fully-assocoative map of 16 words. a. b. 5. Assume a 4-bit arithmatic pipeline which performs 4-bit fix point (integer) addition, realizing 1 bit ofaddition in each stage of pipeline process. Explain and show how this pipeline system can be modified to perform multiple of 4-bit computations (ike 8-bit, 12-bit, etc.) without increasing the stage (dept) of the pipeline