Please answer the questions below:

$5.$ How do beq and j differ, and can you briefly explain how each one is executed in this circuit? Explain the significance of $(2$b$),$ the $$shift left $2.$

$($Hint: Note that there are now two of them, the lower one is familiar and is needed for beq while the upper one is needed for j$.$ What are they doing? Why do we do this shift$-$left i$.$e$.$ multiply by $4?$ It$$s something needed in both cases $...)$

$6.$ Let us suppose the MemToReg control line is defective and gets stuck at $0.$ Which of the supported instructions will always execute correctly? And which ones can possibly execute correctly, and under what circumstances?

$($By $$execute correctly$$ we mean $$produce the correct results, AND do not produce unintended side effects$.$ The processor without a defective control line is the standard for determining correct results and side effects.$)$

$7.$ Look at Instruction$[20$:$16]$ under the instruction lw$.$ These bits specify the target Write register. $($The control signal RegDst is set to $0$ for this purpose.$)$ However, these bits are also fed into Read Register $2.$ So the output bus Read Data $2$ is set with whatever junk value was in the register already. Explain why this unintended read register is not a problem.

$($Hint: we stop this getting into the ALU, and we don$$t set the memory to be ready for a write.$)$