please be solved with the table that includes issue, execution , write back and commit with each clock cycle

Question \#1:Assume we have a processor that implements Tomasulo's algorithin with ROB with the following specifications: - ROB has 8 entries - One common data bus (CDB) - Each functional unt has two reservation stations - Two un-pipelined floating point dividers. Each ane has a latency of 12 clock cycles - Onc 8estage pipelined floating point unit that can perform floating point addtion, substation, and rualtiplication - One 2-staye pipclined load-stote unit Trace the executioe of the follewise code snippet oa this processor. This inchadest - The content of the reservation stations, the register file, and the ROH at each clock cycle * At cach clock cycle, which pipcline stage of which insirsction is executca. - What is the CPl of this code snipect o this processor? fid16,32(2)fldi2,44(3)fmul.df0,f2,f4fstubde48,f2,46fdiv.df0,f0ff6fadd.df6,f8,2