Question: please can i get the vhdl testbench code for this task begin{tabular}{c||c||} Generatorrunning0ontheD-flip-flops & SimilarlytotheshiftregisterinFigure1,buttheoutputQ4isconnectedtotheinputdataofthefirstdischarge(DATA).Thefirsttriggersetsto0whenreset=0andallanothertriggerssetsto1. end{tabular}bitbegin{tabular}{|l||} structural end{tabular}

please can i get the vhdl testbench code for this task

$please can i get the vhdl testbench code for this task \begin{tabular}{c||c||}$

\begin{tabular}{c||c||} Generator"running0"ontheD-flip-flops & SimilarlytotheshiftregisterinFigure1,buttheoutputQ4isconnectedtotheinputdataofthefirstdischarge(DATA).Thefirsttriggersetsto"0"whenreset=0andallanothertriggerssetsto"1". \end{tabular}bit\begin{tabular}{|l||} structural \end{tabular}

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