Please complete this in LOGIC, NOT HDL

5.47 Write a HDL model of a synchronous finite state machine whose output is the sequence , 2,4,6,8 10, 12, 14,0.... The machine is controlled by a single input, Run, so that counting occurs while Run is asserted, suspends while Run is de-asserted, and resumes the count when Run is re-asserted. Clearly state any assumptions that you make. 5.47 Write a HDL model of a synchronous finite state machine whose output is the sequence , 2,4,6,8 10, 12, 14,0.... The machine is controlled by a single input, Run, so that counting occurs while Run is asserted, suspends while Run is de-asserted, and resumes the count when Run is re-asserted. Clearly state any assumptions that you make