Please do the coding in VHDL more important than first part!!!!!

Figure 1 shows a parallel 4-bit parallel Baugh-Wooley multiplier. b b b U a HA HA HA a 0 b; 62 bi bo az a2 ai ao FA FA FA 1 abo agbo ao bi azbo azh a,b2 agb abo a bi ab FA azh az bab2 a3b3 ab ab FA FA DO 1 07 C6 CS C4 C3 c FA FA FA C D D D HA: Half Adder FA: Ful Adder Figure 1. Parallel 4-bit Baugh-Wooley Multiplier 1. Redesign the 4-bit parallel multiplier shown in Figure 1 so it can be used to multiply a 4-bit variable A by a constant K. Each group will re-design the multiplier using the assigned constant K as shown below: 3 1010 2. Write the VHDL code to describe the new 4-bit multiplier design using a suitable design style and simulate it