please do this asap i will definitely upvote your answer ..

II need a the testbench for this code exactly in VHDL prime quartus intel.

Tibrary 1eee; use teee.stdilogic 1164.a11; Ireset, clk, shift_data_in, shift_char_in: in std_logic; data_in, char: in std_logic_vector (1 downto 0); - count: out std_logic_vector (7 downto 0) ); Garchitecture ITCE211_project of sequence_detector is signal receiver, ce: std_logic signa1 para11el_out_data, paraile1_out_char: std_logic_vector(7 downto 0); gcomponent shift_register_data generic C (m: integer:: 8; bport ( clk, reset, shift_data_in: in std_logic; - parallei_out: out std_logic_vector ((m1) downto 0) ); end component; Gcomponent compartor port ( c7k: in std_logic: reset: in std.logic; shift data_in: in std_logic; data in: in std logic vector (1 downto 0); shift_char_in: in std_logic: char: in std iogic vector ( 1 downto 0); - sender: out std_logic ); end component; Ecomponent shift_register_char port C clk:in std_logic; shift_char_in:in'std_logic; reset:in std_logic; char in std_Togic_vector (1 downto 0); -parailel_out: out std_logic_vector (7)downto o) ); end component; Gomponent counter_project generic ( (m: integer:- 8; blart C Ireset, clk, ce: in std_logic; - count: out'stdogic_vector ( ( m-1) downto 0)); end component; begin part_1: shift_register_data generic map (m8,k4) port map (clk clk, reset reset, shift_data_in shift_data_in, data_in data_in, parallel_out para1lel_out_data); part_2: shift_register_char port map (clk clk, reset reset, shift_char_in shift_char_in, char char, para1le1_out paralle1_out_char); part_4: counter_project generic map (m 8,k1 ) port map (clk > cik, reset reset, ce count); port map (clk clk, reset > res: end architecture