Please do this in verilog

The four_bit_adder_subtractor module should be able to add and subtract four bit numbers. As provided, however, it can currently only add. The four_bit_adder_subtractor module takes three inputs: A the first input (four bit) B the second input (four bit) Op the operation (one bit); this will be 0 for addition and 1 for subtraction. Initially, it is ignored within the module. And it yields two outputs: S the sum (four bit) Cout the carry out (one bit) 1 When you run the Verilog simulator, the test bench will notify you if the adder produces unexpected results. Initially, you should see the following output: When subtracting 1 and 1 , got 2 , but expected 0 When subtracting 2 and 5 , got 7 , but expected -3 When subtracting 4 and -4 , got 0 , but expected -8 When subtracting 7 and 7 , got -2 , but expected 0 (The numbers might seem a little funny: the test bench claims that 4 minus 4 should yield 8. This is because in a 4-bit 2s complement number, its impossible to represent 8, the mathemtically correct solution. The bit pattern 1000 will be interpreted as 8.) By modifying the four_bit_adder_subtractor.v file, make it support both addition and subtraction. Do not modify the other files. Your solution must be consistent with the addition algorithm we discussed in class. You may not use Verilogs built-in arithmetic operators. You may use the conditional operator (?:) as a multiplexer. You can use all the basic gates (&, |, ^, ). If youve done it correctly, the test bench shouldnt print out any unexpected results. Submit your corrected four_bit_adder_subtractor.v file, as well as a screenshot (named four_bit_adder_subtractor.png or four_bit_adder_subtractor.jpg) showing the output of GTKWave when viewing the waveform of ports on the corrected four_bit_adder_subtractor module. Make sure that your waveform doesnt contain any red (unknown) values.

Below are the modules:

This is full_adder_module

module full_adder_nodelay(A, B, Cin, S, Cout);

input A, B, Cin;

output S, Cout;

assign S = A ^ B ^ Cin;

assign Cout = (A & B) | (A & Cin) | (B & Cin);

endmodule

This is four_bit_adder_substractor module that needs to be modified

// Include our full adder source file.

`include "full_adder_nodelay.v"

// Define a four-bit ripple carry adder.

//

// Inputs: 4-bit numbers A and B, and Operation

// For the operation, 0 means addition

// 1 means subtraction

// Outputs: 4-bit sum S, carry out bit Cout

//

module four_bit_adder_subtractor(A, B, Op, S, Cout);

// Note the special syntax here to tell the Verilog compiler that A

// and B are not single-bit values, but 4-bit values. These are

// known as arrays in verilog. The 3:0 here indicates we will index

// the bits of A and B from three (MSB) down to zero (LSB).

input [3:0] A;

input [3:0] B;

input Op;

// Similarly, S is a four-bit output. Cout is a one-bit output

output [3:0] S;

output Cout;

// We need three wires to transmit the carry bits between

// the individual full adders.

wire C1, C2, C3;

// Here we are just instantiating four separate full adder modules

// connected by wires.

full_adder_nodelay FA1(A[0], B[0], 1'b0, S[0], C1);

full_adder_nodelay FA2(A[1], B[1], C1, S[1], C2);

full_adder_nodelay FA3(A[2], B[2], C2, S[2], C3);

full_adder_nodelay FA4(A[3], B[3], C3, S[3], Cout);

endmodule // four_bit_rca_nodelay

This is adder_subtractor_test testbench module

// Test bench to compare timing for ripple carry adder and carry

// lookahead adder with simulated propagation delays.

// Tell Icarus Verilog compiler what our timescale is (to interpret

// delay statements).

`timescale 1ns/100ps

`default_nettype none

// Include the module source file for the adder/subtractor

`include "four_bit_adder_subtractor.v"

// Define our testbench module:

module adder_subtractor_test();

// Set up two 4-bit registers A & B for our addends.

reg signed [3:0] A = 4'b0;

reg signed [3:0] B = 4'b0;

// And one for Cin (we will leave it at zero, however).

reg Op = 0;

// Set up two different 4-bit wires to hold results of sums: one

// expected result from built-in Verilog arithmetic, and one

// and one from your module

wire [3:0] S_expected;

wire [3:0] S_actual;

// We're going to ignore Cout here in our tests, but we need to

// define it as an output of our adder/subtractor.

wire Cout;

task check;

input op;

input signed [3:0] a;

input signed [3:0] b;

input signed [3:0] actual;

input signed [3:0] expected;

if (expected !== actual) begin

$display("When %s %d and %d, got %d, but expected %d", op?"subtracting":"adding", a,b,actual,expected);

end

endtask

task test;

input op;

input signed [3:0] a;

input signed [3:0] b;

begin

#20 A = a; B = b; Op = op;

#20 check(op, a, b, S_actual, S_expected);

end

endtask

// The syntax (x ? y : z) here evaluates to "y if x is true, and z otherwise"

assign {S_expected} = Op ? A - B : A + B;

// Instantiate our module for adder/subtractor

four_bit_adder_subtractor adder(A, B, Op, S_actual, Cout);

// This is the behavioral verilog segment to actually run our

// tests. Note we are just setting values of A and B every 20 ticks

// of the clock, and then finishing.

initial begin

$dumpfile("adder_subtractor_test.vcd");

$dumpvars(0, adder_subtractor_test);

#20 test(0, 1, 1);

#20 test(1, 1, 1);

#20 test(0, 2, 5);

#20 test(1, 2, 5);

#20 test(0, 4, -4);

#20 test(1, 4, -4);

#20 test(0, 7, 7);

#20 test(1, 7, 7);

#20 $finish;

end

endmodule