PLEASE DRAW THE HARDWARE FOR A THUMBS UP$,$ THANK YOU!!!

Problem $2$: Appearing below are three variations on a module that will set its output to either

the input value, or a maximum value if the input is larger. The module will always be instantiated

with ul $$ wn$.$ All of them are functionally equivalent, but were synthesized to different costs $($by

Genus $23\mathrm{.}12-$s$086\mathrm{.}1$ when similar code was used in the solution to Homework $3).$ Because they are

functionally equivalent a perfect synthesis program would synthesize each to the same hardware

$($with equal costs$).$

module clamp$\_$plan$\_$a

#$($ int ul $=3,$ wn $=4)($ output u$*$ire $[*$l$-1$:$0]$ x$,$ input uwire $[$wn$-1$:$0]$ a $)$;

localparam logic $[\%$l$-1$:$0]$ nl$\_$max $=*(*$l$)\text{'}(0)$; $//$ Sequence of wl $1$s$.$

assign x $=$ a nl$\_$max $?$ a : nl$\_$max;

endmodule

module clamp$\_$plan$\_$b

#$($ int ul $=3,$ wn $=4)($ output uwire $[$wl$-1$:$0]$ x$,$ input uwire $[$wn$-1$:$0]$ a $)$;

localparam logic $[\%$l$-1$:$0]$ nl$\_$max $=*($wl$)\text{'}(0)$; $//$ Sequence of wl $1$s$.$

assign x $=$ a $$ nl$\_$max $?$ a : nl$\_$max;

endmodule

module clamp$\_$plan$\_$c

#$($ int ul $=3,$ wn $=4)($ output uwire $[*$l$-1$:$0]$ x$,$ input uwire $[$wn$-1$:$0]$ a $)$;

localparam logic $[\%$l$-1$:$0]$ nl$\_$max $=*(*$l$)\text{'}(0)$; $//$ Sequence of wl $1$s$.$

assign x $=!$a$[$wn$-1$:wl$]?$ a : nl$\_$max;

endmodule

Show the optimized hardware for the low$-$cost version$($s$).$

Find the simple$-$model cost of each after optimization. The costs should be

wl$.$

in terms of un and

Find the simple$-$model delay of each after optimization. The delays should be

and wl$.$