please explain what each line of code does, and verify by running code. thank you! the language is system verilog

What is the output of variable "data" at the end of simulation? module datatype_2O bit [3:01 data; initial begin system("clear: echo; echo") data= { 32{4"b1111} }; $display ("data: %d", data ) ; 100; sdisplay(nn") finish; end endmodule Numeric