PLEASE FILL IN BLANKS I NEED HELP, PLEASE.

2. Build a Half Adder Below is the circuit and Boolean equations for a Half Adder. In this part, we will design the half adder structurally using basic logic gates, exactly following the topology of the circuit diagram. Edit the definition of halfadder to make it purely structural as follows. A skeleton of the Verilog description is provided, with some details missing. Your task to fill in the blan below. is Ks. Be sure that your Verilog description exactly matches the circuit module halfadder (S, C. X, y): xt Al input x. y: output S. C; A2 /Instantiate primitive gates xor AIC-,--, and A20 endmodule Alternatively, you can use dataflow modelling by expressing each output as a Boolean equation in Verilog: assign S assign C Or you can use behavioral modelling assign {C,S}=