$($PLEASE FINISH FAST, ASSIGNMENT DUE IN $1$ HOUR$)2.(3$ pts$)$ Design a $"11011"$ sequence detector $($Mealy FSM$).$ This circuit produces an output of $1$ when the sequence $11011$ is received. For any other input sequence the output is zero. Use JK FFs and show all design steps. $[$Hints: use the following state definitions and state assignments. S$0(=\backslash (000)=\backslash )$ "reset" state i$.$e$.$ no $1$ has passed through the circuit. S$1\backslash ((=001)=\backslash )$ state of the circuit when a single $1$ is received. S$2\backslash ((=011)=\backslash )$ state of the circuit when the sequence $11$ is received. S$3\backslash ((=100)\backslash )\backslash (=\backslash )$ state of the circuit when the sequence $110$ is received and finally S$4\backslash ((=101)=\backslash )$ state of the circuit when the sequence $1101$ is received. The states $010,110$ and $111$ are unused.$]$