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Exercise 4.1 Sketch a schematic of the circuit described by the following HDL code. Simplify the schematic so that it shows a minimum number of gates. VHDL library IEEE; use IEEE. STD_LOGIC_1164. all; Verilog module exercisel (input a, b, c, output y, z): assign y = a b c ! Sba &c: assign z = a&b --: endmodule entity exercisel is port(a, b, c in STD_LOGIC; y. 2: out STR_LOGIC): end: architecture synth of exercisel is begin y